Semiconductor memory device capable of efficient memory cell select operation with reduced element count

ABSTRACT

Four subordinate word lines are driven for a single main word line. In a subordinate word driver circuit, a bank select line activated allows a potential level of a main word line to be transmitted to an internal node via a first transistor. Simultaneously, a select line is also active and a potential level of the internal node is transmitted to a subordinate word line via a second transistor. A bank select line is inactivated and the select line is then further boosted to a boosted potential so that it is driven to a boosted potential of a potential level of the subordinate word line.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor memory devices andparticular to configurations of a memory cell select circuit and thoseof a redundant circuit thereof.

[0003] 2. Description of the Background Art

[0004] In recent years, as microprocessors (MPUs) are improved inoperating speed, there has been used synchronous DRAM (SDRAM) operatingin synchronization with a clock signal to achieve rapid access e.g. of adynamic random access memory (DRAM) used as a main memory device.

[0005] Internal operation of such an SDRAM and the like is divided intorow-and column-related operations for control.

[0006] The SDRAM and the like also employ a bank configuration, thememory cell array divided into banks each capable of independentoperation, to achieve further rapid operation. More specifically, foreach bank, the operation is controlled independently with respect to therow-and column-related operations.

[0007] Typically, a word line is hierarchically configured by main andsubordinate word lines to reduce the load to be driven by a drivecircuit to provide for rapid operation in the operation of selecting arow of the memory cell array or a word line in the row-relatedoperation.

[0008] In semiconductor memory devices such as an SDRAM and the likehaving a conventional multibank configuration, however, the hierarchicalconfiguration described above disadvantageously results in an increasednumber of the elements required for selecting a subordinate word line.

[0009] Furthermore, in recent years a memory circuit and a logic circuitare integrated on a single chip to provide e.g. chips on which a DRAMand a logic circuit are mounted mixedly for the purpose of achievingmultifunction, improving data processing speed and the like. For thistype of chips, the data bus width for communicating data between astorage device such as a DRAM and a logic circuit that are integrated ona single chip, i.e., the number of bits of data communicated at onetime, tends to be increased to provide rapid process.

[0010] Furthermore, an input/output line (an I/O line pair) transmittingdata read from a memory cell to an interface circuit is often configuredhierarchically in view of enhancement of operating speed and the like.To transmit data from a memory cell via the hierarchical I/O line pair,a gate circuit is provided therebetween for selectively connecting a bitline pair connected to the memory cell selected in a read operation andthe I/O line pair communicating the data. For multibank, memory cellarrays, such a gate circuit also tends to be increased in the number ofelements used therefor. Particularly, inputting and outputting data on abus with such a large bus width as described above requires an increasednumber of independently operable I/O line pairs. This also increases thenumber of the gate circuits described above and hence the number ofelements configuring the gate circuits.

SUMMARY OF THE INVENTION

[0011] An object of the present invention is to provide a semiconductormemory device with a memory cell array capable of efficient selectoperation with reduced number of the elements of a circuit for selectinga memory cell in the memory cell array.

[0012] Another object of the present invention is to provide asemiconductor memory device with a memory cell array configurationcapable of reducing the number of elements used for a data communicationpath for reading data.

[0013] The present invention is a semiconductor memory device includinga memory cell array, a plurality of main word lines, a plurality ofsubordinate word lines, a main row select circuit, a subordinate rowselect circuit, a block select circuit, a plurality of block selectlines, and a plurality of drive circuits.

[0014] The memory cell array has a plurality of memory cells arranged inrows and columns. The memory cell array is divided into a plurality ofmemory cell blocks in rows and columns.

[0015] The plurality of main word lines are arranged in the direction ofthe rows of the memory cell array, shared by a plurality of memory cellblocks arranged in the direction of the rows of the memory cell array.The plurality of subordinate word lines correspond to respective rows ofmemory cells in the memory cell blocks such that a first plurality ofthe plurality of subordinate word lines are provided for each main wordline. The main row select circuit is provided for the memory cell arrayand selectively activates a main word line in response to an addresssignal. The subordinate row select circuit is provided for the memorycell array, indicating which subordinate word line is activated out ofthe first plurality of subordinate word lines in response to an addresssignal. The block select circuit responds to an address signal toindicate which memory cell block has been selected. The plurality ofblock select lines are activated in response to an indication of blockselection from the block select circuit.

[0016] The plurality of drive circuits are each provided for asubordinate word line, driving a potential of the associated subordinateword line in response to an indication from the subordinate row selectcircuit and activation of the associated block select line andactivation of the associated main word line.

[0017] Each drive circuit includes a first switch circuit transmitting apotential level from a main word line in response to activation of ablock select line, and a hold circuit activated in response to an outputlevel of the switch circuit and an indication from the subordinate rowselect circuit to hold selection-indicating information for anassociated subordinate word line and drive a potential of the associatedsubordinate word line.

[0018] The main row select circuit and the block select circuit reset alevel of a main word line and a level of a block select line after theselection-indicating information is completely transmitted to the holdcircuit.

[0019] In another aspect of the present invention, a semiconductormemory device includes a memory cell array, a row select circuit, ablock select circuit, a plurality of redundant memory cell blocks, and aredundancy determination circuit.

[0020] The memory cell array has a plurality of memory cells arranged inrows and columns. The memory cell array is divided into a plurality ofmemory cell blocks in rows and columns.

[0021] The row select circuit is provided for the memory cell array,selecting a row of memory cells in response to an address signal. Theblock select circuit responds to an address signal to indicate whichmemory cell block has been selected.

[0022] The plurality of redundant memory cell blocks are providedindependently of the memory cell blocks. The redundancy determinationcircuit previously stores a memory cell block and address at which adefective memory cell is located and the redundancy determinationcircuit selects a redundant memory cell within a redundant memory cellblock when a memory cell designated according to an address signalcorresponds to the defective memory cell.

[0023] In accordance with the present invention, the memory cell arraycan be advantageously divided and thus operated to reduce electricityconsumption. Furthermore, the divided memory cell blocks arranged inrows and columns can enhance the degree of freedom in circuitconfiguration when multibit data are communicated concurrent1y.

[0024] Still advantageously, in accordance with the present invention aredundant memory cell in the redundant memory cell blocks providedindependently of the memory cell array can be substituted for adefective memory cell to enhance the efficiency with which the redundantmemory cell is substituted for the defective memory cell.

[0025] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a schematic block diagram showing a configuration of asemiconductor memory device 1000 according to a first embodiment of thepresent invention.

[0027]FIG. 2 is a schematic block diagram showing a configuration of amemory cell array.

[0028]FIG. 3 is a circuit diagram for illustrating a detailedconfiguration of a subordinate word driver band BSDRn.

[0029]FIG. 4 is a circuit diagram showing a configuration connecting asense amplifier portion and a data line portion together.

[0030]FIG. 5 is a timing diagram for illustrating an operation of thesemiconductor memory device according to the first embodiment.

[0031]FIG. 6 is a circuit diagram showing a configuration connectingtogether a sense amplifier portion and data line portion of asemiconductor memory device according to a second embodiment.

[0032]FIG. 7 is a timing diagram for illustrating a read operation ofthe FIG. 6 circuit.

[0033]FIG. 8 is a timing diagram for illustrating write and prechargeoperations of the FIG. 6 circuit.

[0034]FIG. 9 is a circuit diagram showing a configuration connectingtogether a sense amplifier portion and data line portion of amodification of the second embodiment.

[0035]FIG. 10 is a timing diagram for illustrating a read operation ofthe FIG. 9 circuit.

[0036]FIG. 11 is a timing diagram for illustrating write and prechargeoperations of the FIG. 9 circuit.

[0037]FIG. 12 is a schematic block diagram for illustrating aconfiguration of a redundant circuit according to a third embodiment ofthe present invention.

[0038]FIG. 13 is a schematic block diagram showing another example ofthe redundant circuit according to the third embodiment of the presentinvention.

[0039] FIGS. 14 to 17 are first to fourth conceptual views forillustrating shift redundancy circuit operation.

[0040] FIGS. 18 to 21 are first to fourth circuit diagrams forillustrating shift redundancy circuit operation.

[0041]FIGS. 22 and 23 are conceptual views for illustrating shiftredundancy circuit operation.

[0042]FIG. 24 is a circuit diagram for illustrating a configuration ofcircuitry controlling a shift redundancy circuit.

[0043]FIG. 25 is a schematic block diagram for illustrating aconfiguration of redundant circuit according to a fourth embodiment.

[0044]FIG. 26 is a circuit diagram for illustrating a configuration ofBAP and RAC portions in a redundancy determination portion 3010.

[0045]FIG. 27 is a circuit diagram for illustrating a configuration ofRAP and RAC portions in redundancy determination portion 3010.

[0046]FIG. 28 is a schematic block diagram for illustrating aconfiguration of an HIG portion in redundancy determination portion3010.

[0047]FIG. 29 is a first circuit diagram for illustrating aconfiguration of a column bank match determination circuit 3110.

[0048]FIG. 30 is a second circuit diagram for illustrating aconfiguration of column bank match determination circuit 3110.

[0049]FIG. 31 is a schematic block diagram for illustrating aconfiguration of a redundant row.

[0050]FIGS. 32 and 33 are fist and second schematic block diagrams forillustrating configurations of a word line drive circuit, respectively.

[0051] FIGS. 34 to 38 are first to fifth schematic block diagrams,respectively, for illustrating configurations of a column selectcircuit.

[0052] FIGS. 39 to 42 are first to fourth schematic block diagrams,respectively, for illustrating data line arrangements.

[0053] FIGS. 43 to 60 are schematic block diagrams for illustratingfirst to eighteenth examples, respectively, of a row-selection-relatedcircuit, a column-selection-related circuit and adata-input/output-related circuit when banks are arranged in rows andcolumns.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] First Embodiment

[0055]FIG. 1 is a schematic block diagram showing a configuration of asynchronous semiconductor memory device 1000 according to a firstembodiment of the present invention. It should be noted that, as will bedescribed below, the present invention is not limited to such asynchronous semiconductor memory device and is applicable to generalconfiguration of semiconductor memory device memory cell array.

[0056] Referring to FIG. 1, an SDRAM 1000 includes an external clocksignal input terminal 1002 receiving externally applied, complementaryclock signals EXT.CLK and EXT.CLK, clock input buffers 150, 152buffering the clock signals input to external clock terminal 1002, aninternal control clock signal generation circuit 1008 receiving outputsfrom clock buffers 150, 152 to generate an internal clock signalINT.CLK, and a mode decoder 1022 receiving an external control signalfrom an external control signal input terminal 1010 via input buffers1012 to 1020 operating in response to internal clock signal INT.CLK.

[0057] Internal control signal input terminal 1010 receives a signalCKE, a chip select signal/CS, a row address strobe signal/RAS, a columnaddress strobe signal/CAS, a write control signal/WE, and data masksignals DM0 to DM3.

[0058] Signal CKE is a signal for indicating that inputting a controlsignal to a chip is enabled. When the signal is inactive, inputting acontrol signal is not permitted and SDRAM 1000 does not operate.

[0059] Signal/CS is a signal for determining whether a command signalhas been input. With this signal active (low), at a rising edge of aclock signal a command is determined depending on a combination oflevels of other control signals.

[0060] Signal/RAS is a signal indicative of operation of a row-relatedcircuit and signal/CAS instructs that operation of a column-relatedcircuit be activated. Signal/WE is a signal for distinguishing betweenwrite and read operations.

[0061] Signals DM0 to DM3 are signals indicative of operation maskingdata communication with respect to data input/output terminals DQ0-DQ7,DQ8-DQ15, DQ16-DQ23, DQ24-DQ31, respectively.

[0062] Mode decoder 1022 responds to the external control signals tooutput an internal control signal for controlling operation of aninternal circuit of SDRAM 1000. Mode decoder 1022 outputs e.g. signalsROWA, COLA, ACD, PC, READ, WRITE, APC, SR, as internal control signals.Signal ROWA indicates that row-related access is performed. Signal COLAindicates that column-related access is performed. Signal ACT indicatesthat a word line is activated.

[0063] Signal PC instructs precharge operation to indicate thatoperation of the row-related circuit is completed. Signal READ instructsthe column related circuit to perform read operation. Signal WRITEinstructs the column-related circuit to perform write operation.

[0064] Signal APC indicates auto-precharge operation. Whenauto-precharge operation is designated, simultaneously with completionof a burst cycle a precharge operation is started automatically. SignalSR indicates self-refresh operation. When self-refresh operation isstarted a self-refresh timer operates, and when a predetermined periodof time has elapsed since the initiation of the timer operation a wordline is activated to start refresh operation.

[0065] SDRAM 1000 also includes a self-refresh timer 1054. Timer 1054starts to operate when signal SR designates a self-refresh mode. When apredetermined period of time has elapsed since the initiation of thetimer operation, timer 1054 instructs that a word line be activated orrefresh operation be started. SDRAM 1000 also includes a refresh counter1056 for generating an address for performing a refresh operationaccording to an indication from self-refresh timer 1054.

[0066] SDRAM 1000 also includes a reference potential input terminal1022 receiving a signal VREF serving as a reference for determiningwhether an input signal is a high level signal or a low level signal, amode register 1046 responsive to an address signal applied via addresssignal input terminal 1030 and a combination of the above-describedexternal control signals for holding information on a predetermined modeof operation, such as information on data for burst length, informationon which one of single and double data rate operations has beendesignated, a row address latch 1048 receiving an address signal viaaddress signal input buffers 1032-1038 operating in response to internalclock signal INT.CLK and holding an input row address at row-addressinput timing, a column address latch 1050 receiving address signalsA0-A12 and holding a column address at a timing at which the columnaddress is input, a multiplexer 1058 receiving an output from refreshaddress counter 1056 and an output from row address latch 1048 andselectively outputting the output from row address latch 1048 in normaloperation and the output from refresh address counter 1056 inself-refresh operation, a row predecoder 1062 receiving an output frommultiplexer 1058 to predecode a row address, a burst address counter1060 referring to a column address held in column address latch 1050 togenerate an internal column address depending on burst-length data frommode register 1046, a column predecoder 1064 receiving an output fromburst address counter 1060 to predecode a corresponding column address,a bank address latch 1052 receiving bank addresses BA0-BA3 from anaddress input terminal via input buffers 1040-1044 operating in responseto internal clock signal INT.CLK, and holding a bank address valuedesignated, and a bank decoder 1066 receiving an output from bankaddress latch 1052 to decode a bank address.

[0067] Bank address signals BA0-BA3 indicate an accessed bank in each ofrow-related access and column-related access. More specifically, in eachof row- and column-related accesses, bank address signals BA0-BA3 inputto address signal input terminal 1030 are initially taken into bankaddress latch 1052 and then decoded by bank decoder 1066 before they aretransmitted to each memory array block (or bank).

[0068] SDRAM 1000 also includes a memory cell array 1100 includingmemory array blocks operating as banks 0 to 15 each as a unit capable ofread/write operation independently, a main row decoder 2142 responsiveto an output from bank decoder 1066 and an output from row predecoder1062 for selecting a row (or word line) in a corresponding bank, a maincolumn decoder 2104 responsive to an output from column predecoder 1064for selecting a column (or bit line pair) in a corresponding bank, anI/O port 2152 supplying data read from a selected memory cell of aselected bank to a global I/O bus G-I/O in read operation and supplyingwrite data transmitted from bus G-I/O to a corresponding bank in writeoperation, a data input/output circuit 1086 holding externally appliedwrite data and supplying the write data to bus G-I/O in write operationand holding read data transmitted from bus G-I/O in read operation, andbidirectional input/output buffers 1072-1082 for communicatinginput/output data DQ0-DQ31 between data input/output circuit 1086 anddata input/output terminal 1070.

[0069] In memory cell array 1100, banks 0 to 15 are arranged in fourrows and four columns. It should be noted that the arrangement of thebanks is not limited as described above and more banks may be arranged.More specifically, banks may be arranged in a matrix of the mxn, whereinm and n each represent a natural number.

[0070]FIG. 2 is a schematic block diagram for illustrating in detail aconfiguration of the FIG. 1 memory cell array 1100.

[0071] Referring to FIG. 2, memory cell array 1100 is divided intomemory cell array units (or banks) surrounded by sense amplifier bandand subordinate word line driver band. Memory cell array 1100 isactivated for each memory cell array unit.

[0072] A main word line MWL is provided across memory cell array units,activating a subordinate word driver SWD required to be activated. Whensubordinate word driver SWD is activated, the associated subordinateword line SWL is responsively activated. Sense amplifiers arealternately arranged such that they sandwich memory cell array units.

[0073] Also, a sense amplifier is activated which belongs to a region atwhich a select line for a region (or bank) to be activated and a senseselect line cross.

[0074] Along the direction of word lines of memory cell array units, asegment YS line traverses a sense amplifier band.

[0075] In reading data from a memory cell array unit, segment YS lineSGYS activated allows activation of a region (or a bank) at whichsegment YS line SGYS and a bank select line activated cross. From theactivated region (or bank), one data is read e.g. for four senseamplifiers.

[0076] The read data is transmitted to a read/write amplifier (referredto as an R/W amplifier hereinafter) 2154 via a data line pair running onthe memory cell array in a direction orthogonal to word lines.

[0077] Then via a peripheral circuit, a data bus region and the like,the read data is transmitted to a data output portion. For a chip onwhich memory and logic are mounted mixedly, data is transmitted to alogic portion via a data bus region.

[0078] More specifically, memory cell array 1100 has memory mats (orbanks) arranged in four rows and four columns. For each row is provideda group of main word drivers included in a main row decoder 2142, andfor each column is provided an I/O selector 2152. Each memory mat (orbank) is provided with a sense amplifier band 2148 and a subordinateword driver band 2150.

[0079] Row-related select operation will first be described. In responseto a row address signal, a main word driver 2156 selectively activatesmain word line MVL. Also an SD driver 2144 activates a segment decodeline SGDL (including a bank select line BSL and a select line SL, and areset line RSL). By main word line MWL and segment decode line SGDL anassociated subordinate word driver 2168 is activated and responsively asubordinate word line 2170 is activated and an access transistorconnected to a selected memory cell is turned on. It should be notedthat select line SL corresponds to four select lines SL0-SL3collectively.

[0080] It should also be noted that reset line RSL corresponds to fourreset lines RSL0-RSL3 collectively.

[0081] Responsively, data is output on a bit line pair 2158 provided fora selected column of memory cells.

[0082] Select operation in the column direction will now be described. Asegment YS driver 2160 activates segment YS line SGYS. It should benoted that segment YS lines SGYS includes four read source linesRGL0-RGL3 and four write activation lines WRL0-WRL3. The activated SGYSline allows a selectively associated I/O gate 2162 to be activated sothat one of the signals output from four sense amplifiers is thus outputexternally via an I/O line 2164.

[0083] It should be noted read source lines RGL0-RGL3 are collectivelyreferred to as a read source line RGL and write activation linesWRL0-WRL3 are collectively referred to as a write activation line WRL.

[0084]FIG. 3 is a diagram for showing a detailed configuration of theFIG. 2 subordinate word driver band BSDRn.

[0085] A driver circuit 8000 includes a select transistor 8100 havingits gate controlled by bank select line BSL and provided between a mainword line and an internal node N1, a transistor 8102 having its gateconnected to node n1 and connected between one select line SL0 of selectline SL and subordinate word line SWL, and a transistor 8104 having itsgate potential controlled by the same select line SL0 as transistor 8102and connected between subordinate word line SWL and node n1. A drivercircuit 8000 also includes a transistor 8106 having its gate potentialcontrolled by reset line RSL0 and provided between a subordinate wordline and ground potential.

[0086] Other main and subordinate word lines are configured similarly.

[0087] With this configuration, main word line MWL activated and bankselect line BSL activated and any of select lines SL activated allowword line SWL to be activated (or attain high potential) and reset lineRSL selectively activated allows associated subordinate word line SWL tobe discharged to ground potential.

[0088] In the FIG. 3 example, a single main word line MWL controls foursubordinate word lines SWL in each bank and which one of subordinateword lines SWL is selected is designated depending on the activation ofone of select lines SL.

[0089] Bank select line BSL attains the level of a boosted potential Vppwhen it is activated, and transitions to the level of a ground potentialVss when subordinate word line SWL is activated, while a latch circuitconfigured by transistors 8102 and 8104 holds the active state of bankselect line BSL. The potential level of select line SL and that of resetline RSL are controlled to be complementary to each other.

[0090] For standby operation, bank select line BSL is held at the groundpotential (GND) level, select line SL at the ground potential (GND)level, and reset line RSL at the power supply potential (Vcc) level.

[0091] For activation operation, an associated reset line is initiallyset to ground potential (GND) and bank select line BSL corresponding tosubordinate word line SWL to be activated is activated so that thepotential level is equal to the boosted potential Vpp level.

[0092] Main word line MWL is then activated to the power supplypotential (Vcc) level. Almost simultaneously with the activation of mainword line MWL, one of select lines SL attains the power supply potential(Vcc) level and subordinate word line SWL attains a level of Vcc minusVth. Bank select line BSL then transitions to the ground potential (GND)level and electrical charge is thus confined in a latch circuit in adriver circuit 8000.

[0093] With the electrical charge confined by transistors 8102 and 8104,when the potential level of the selected one of select lines SL isboosted to the boosted potential (Vpp) level the level of subordinateword line SWL can change until it reaches the boosted potential (Vpp)level.

[0094] For reset operation, the potential level of the bank select lineis increased to the power supply potential (Vcc) level and select lineSL is set to the ground potential (GND) level. Also, a reset line is setto the power supply potential (Vcc) level to discharge the electricalcharge stored in subordinate word line SWL.

[0095] With this configuration, subordinate word line driver 8000 can beconfigured only by four n-channel MOS transistors and thus reduced inthe number of the elements configuring the same.

[0096] As will be described hereinafter, activation of a main word lineis provided as a one-shot pulse signal. More specifically, oncetransistors 8102 and 8104 in subordinate word driver 8000 associatedwith a selected subordinate word line hold an active state of a mainword line, the potential level of the main word line is reset. With thisconfiguration, if a plurality of banks are arranged in the direction ofthe main word line, as shown in FIG. 2, the potential level of the mainword line does not affect subordinate word driver 8000, as long as bankselect line BSL is not activated. Thus, two banks adjacent to each otherin the row direction as shown in FIG. 2 can be operated independently.

[0097]FIG. 4 is a circuit diagram showing a configuration providing aconnection between a sense amplifier portion and a data line portion.

[0098] An input/output node of a sense amplifier is such configured thata data signal is transmitted via gate-receiving transistors 8400 and8402 and a pair of data lines DL and /DL.

[0099] More specifically, transistors 8400 and 8402 have theirrespective sources set by read source line RGL to a ground potentialselectively, their respective gates each connected to a respective senseamplifiers S/A at a respective input/output node, and the respectivedrains each connected to a respective pair of data lines DL and /DL.

[0100] According to the FIG. 4 configuration, four sense amplifiersshare a single pair of data lines DL and /DL.

[0101] The pair of data lines DL and /DL in write operation areselectively connected by transistors 8500 and 8502 respectivelyconnected between an associated bit line BL and data line DL and betweenbit line /BL and an associated data line /DL.

[0102] More specifically, the input/output nodes of sense amplifiersS/A0 to S/A3 respectively associated with pairs of bit lines BL0 and/BL0 to BL3 and /BL3 are selectively connected to the pair of data linesDL and /DL by transistors 8500 and 8502 having gate potential controlledby the respective write activation line WRL0 to WRL3.

[0103] The FIG. 2 segment YS includes read source line RGL (referring toread source lines RGL0-RGL3 collectively), write activation line WRL(referring to write activation lines WRL0-WRL3 collectively), and thelike, as has been described above.

[0104] With the configurations described above, in data read operationthe pair of data lines DL and /DL and an input/output node of anassociated sense amplifier are not connected together directly and thetransistors 8400 and 8402 gates driven depending on a potential level ofthe input/output node of the sense amplifier allow the level of dataline pair DL and /DL to be changed. Thus, if selecting a memory cellcolumn in response to a column address signal, i.e., an operation ofselecting any of read source lines RGL0-RGL3 and an amplificationoperation by a sense amplifier overlap or the select operationanticipates the amplification operation, read operation can be performedwithout data destruction.

[0105] This means that read operation can rapidly be performed asdescribed above. Furthermore, sense amplifier activation is onlyrequired for each limited region. Thus, the peak value of operatingcurrent can be reduced to obtain such effects as reduction in powerconsumption, noise reduction and the like.

[0106]FIG. 5 is a timing diagram for representing an operation of theSDRAM 1000 described above.

[0107] Referring to FIG. 5, at the activation edge of external clocksignal EXT.CLK at time t1 are provided address signals VBA and HBA invertical and horizontal directions, respectively, of the banks arrangedin four by four as shown in FIG. 2.

[0108] Responsively, at time t2, bank select line BSL is activated as aone-shot signal in response to bank address signal HBA in the horizontaldirection and segment YS line SGYS is activated in response to bankaddress VBA in the vertical direction, and a signal FLAG is activated ina local control circuit provided for each bank, indicating that aselected bank is activated. When bank select line BSL is activated,transistor 8110 is responsively turned on.

[0109] Furthermore at time t2 an equalization signal EQ indicative ofoperation equalizing paired bit lines, paired I/O lines and the like,and reset signal RSL for resetting the level of a subordinate word lineare inactivated low.

[0110] At time t3, in response to a row address signal, main word lineMWL is selectively activated to power supply voltage Vcc, and almostsimultaneously one of select lines SL is selectively activated to theVcc level.

[0111] At time t4, bank select line BSL attains an inactive level (a GNDlevel) while select line SL is driven to the boosted potential Vpplevel. Responsively, selected subordinate word line SWL is also drivento the boosted-potential level.

[0112] At time t4, sense amplifier activation signal SE is alsoactivated to amplify data read from a memory cell connected to selectedsubordinate word line SWL.

[0113] At time t5 main word line MWL is inactivated and at time t6select line SL is inactivated, while selected subordinate word line SWLis maintained at the active level (the Vpp level).

[0114] While sense amplifier activation signal SE from the outside ofmemory cell array 1100 is inactivated at time t6, sense amplifieractivation signal 1SE remains active in a selected bank.

[0115] At the activation edge of external clock signal EXT.CLK at timet7 are applied vertical and horizontal address signals VBA and HBA ofthe banks arranged 4 by 4 that are different from those applied at timet1. Thereafter for the selected bank a series of operations similar tothose performed from times t1 to t6 are performed to provide readoperation.

[0116] Furthermore, at the activation edge of external clock signalEXT.CLK at time t8 are applied vertical and horizontal address signalsVBA and HBA of the bank arranged in 4 by 4 that are different from thoseapplied at times t1 and t7. Thereafter for the selected bank a series ofoperations similar to those performed from times t1 to t6 are providedto perform read operation.

[0117] At time t10, vertical and horizontal address signals VBA and HBAare applied to designate a bank subjected to a reset operation.Responsively, bank select line BSL selected is activated at time t11 andflag signal FLAG indicative of bank activation is also inactivated.

[0118] Then, when reset line RSL attains an active level at time t12,subordinate word line SWL responsively attains an inactive level.Meanwhile, the sense amplifier activation signal is inactivated andequalization signal EQ is then activated to complete the resetoperation.

[0119] Thereafter, again in response to an external bank address signala bank is selected and activated.

[0120] The configuration as described above can reduce the number oftransistors configuring a subordinate word driver, with a memory cellarray divided into memory cell array units arranged in row and columndirections and operating as banks and with word lines operatinghierarchically.

[0121] Second Embodiment

[0122]FIG. 6 is a circuit diagram showing a configuration connectingtogether a sense amplifier portion and data line portion of asemiconductor memory device according to a second embodiment of thepresent invention, compared with the first embodiment of FIG. 4.

[0123] In FIG. 6, eight pairs of bit lines BLL0 and /BLL0 to BLL3 and/BLL3 and BLR0 and /BLR0 to BLR3 and /BLR3 share a single I/O line pair,although the present invention is not limited to this configuration andmore bit line pairs may share a single I/O line pair.

[0124] In FIG. 6, a sense amplifier S/A0 and an equalization circuitEQCKT0 are shared by a pair of bit lines BLL0 and /BLL0 on the left sideand a pair of bit lines BLR0 and /BLR0 on the right side. Senseamplifier S/A0 and equalization circuit EQCKT0 are selectively coupledwith the pair of bit lines BLL0 and /BLL0 via transistors TRL10 andTRL20 controlled by a signal BLIL, and sense amplifier S/A0 andequalization circuit EQCKT0 are selectively coupled with the pair of bitlines BLR0 and /BLR0 via transistors TRR10 and TRR20 controlled by asignal BLIR.

[0125] A sense node of sense amplifier S/A0 is coupled with a segmentI/O line pair SGI/O via transistors TRG1 and TRG2 each controlled bysegment decode line SG0.

[0126] Data on segment I/O line pair SGI/O is selectively transmitted toan I/O line pair via a read/write gate R/WCKT.

[0127] Read/write gate R/WCKT includes a transistor TDC1 having its gateconnected to one segment I/O line SGI/O1 of the segment I/O line pairand having its source coupled with a ground potential GND, a transistorTDC2 having its gate connected to the other segment I/O line SGI/O2 ofsegment I/O line pair SGI/O and having its source coupled with groundpotential GND, a transistor TRI1 provided between the transistor TDC1drain and one I/O line I/O2 of the I/O line pair and having a gatepotential controlled by a signal R-CSL, a transistor TRI2 providedbetween the transistor TDC2 drain and the other I/O line I/O1 of the I/Oline pair and having a gate potential controlled by signal R-CSL, atransistor TWC2 having its gate connected to one I/O line I/O1 of theI/O line pair and having its source coupled with ground potential GND, atransistor TWC1 having its gate connected to the other I/O line I/O2 ofI/O line pair I/O and having its gate coupled with ground potential GND,a transistor TWI1 provided between the transistor TWC1 drain and segmentI/O line SGI/O line I/O1 and having a gate potential controlled by asignal W-CSL, a transistor TWI2 provided between the transistor TWC2drain and segment I/O line SGI/O2 and having a gate potential controlledby signal W-CSL, a transistor TPC1 provided between segment I/O lineSGI/O1 and ground potential GND and having a gate potential controlledby an equalization signal IOEQ, and a transistor TPC2 provided betweensegment I/O line SGI/O2 and ground potential GND and having a gatepotential controlled by equalization signal IOEQ.

[0128] Other pairs of bit lines BLL1 and /BLL1 and BLR1 and /BLR1 toBLL3 and /BLL3 and BLR3 and /BLR3 are provided with respective senseamplifiers, equalization circuits, gate transistors and the like similarto those for the pair of bit lines BLL0 and /BLL0.

[0129]FIG. 7 is a timing diagram for illustrating an operation of acircuit providing a connection of the sense amplifier portion and dataportion represented in FIG. 6.

[0130] Referring to FIG. 6, in the standby state at time t0 a bit linepair is precharged to a level of ½ Vcc while segment I/O line pair SGI/Ois precharged to the GND level in response to signal IOEQ activatedhigh. Segment decode lines SG0-SG3 are all held at ground potential GNDand transistors TRG1 and TRG2 for all bit line pairs are disconnected.

[0131] Signals BLIL and BLIR for opening and dosing the connectionbetween a bit line pair and sense amplifier S/A configuring a so-calledshared sense amplifier are held at an intermediate potential (apotential intermediate between power supply potential Vcc and boostedpotential Vpp).

[0132] The bit line equalization signal is active high and the I/O linepair is precharged to power supply potential Vcc.

[0133] It should be noted that signals BLIL and BLIR are held at theintermediate potential so as to reduce a potential applied to the gatesof transistors TRL1, TRL2, TRR1 and TRR2 controlled by signals BLIL andBLIR. It should be noted, however, that they are set at an intermediatepotential no less than power supply potential Vcc, since the potentialsof the bit line pair are required to be equalized.

[0134] At time t1, signal BLIL transitions to boosted potential levelVpp and signal BLIR to ground potential GND to select left-side bit linepairs BLL0 and /BLL0 to BLL3 and /BLL3.

[0135] At time t2, equalization signals EQ and IOEQ start to transitiontoward ground potential GND. When at time t3 the level of segment decodeline SG0 exceeds a threshold value of transistor TRG1, TRG2, the pair ofbit lines BLL0 and /BLL0 and the pair of segment I/O lines SGI/O1 andSGIO/02 are connected together so that potential level of the bit linepair drops below the precharge level of ½ Vcc while that of the segmentI/O line pair starts to rise exceeding the precharge level or potentialGND.

[0136] At time t4, when the difference between the potential level ofthe bit line pair and that of word line WL exceeds a threshold value ofaccess transistor TA, a difference is caused between the potential levelof bit line BLL0 and that of complementary bit line /BLL0, depending onthe data held in memory cell capacitor MC. Similarly, a potentialdifference is caused in segment I/0 line pair SGI/O. At time t5, thepotential level of the word line increases to the intermediatepotential. It should be noted that the potential level of the word lineis not required to be increased to boosted potential Vpp, since thepotential level of the bit line pair immediately before data is readfrom the memory cell capacitor is smaller than ½ Vcc. In other words,data is read out on a bit line pair with a word line lower in potentiallevel than when data is read with the potential level of the bit linepair started from ½ Vcc. This can increase data reading speed.

[0137] At time t6, when signal R-CSL is activated the potential level ofthe I/O line pair, at the precharge level is driven and thus changed bytransistors TDC1 and TDC2 depending on the potential level of thesegment I/O line pair. Thus data is read onto the I/O line pair.

[0138] It should be noted that signal R-CSL may be activated at a timingmuch earlier than time t6. This is because segment I/O line pair SGI/Oand the I/O line pair are not connected together directly and even insuch a case as described above the data held in a memory cell is notdestroyed due to the potential level of the I/O line pair.

[0139] The potential difference of the bit line pair is also amplifiede.g. at time t7 by an activated sense amplifier and data is thusrestored in a memory cell. As has been described above, it is notnecessary to use data amplified by a sense amplifier in reading dataonto an I/O line pair. Thus, if the sense amplifier operates slowly, itdoes not affect data reading speed. Accordingly, the size of the senseamplifier is only required to be that sufficient to ensure that data canbe restored and the sense amplifier can thus be reduced in layout area.It should be noted that when the amplitude of the amplificationpotential of the sense amplifier after time t7 is set at a potentialintermediate between power supply potential Vcc and ground potential GNDrather than adapted to fully swing to power supply potential Vcc, theelectrical charge held in other non-selected memory cells connected tothe bit line pair is not lost due to noise caused in the bit line pair.

[0140] Data write operation and precharge operation will now bedescribed.

[0141]FIG. 8 is a timing diagram for representing an operation of acircuit which provides the FIG. 6 connection between a sense amplifierportion and a data line portion in the write and precharge operations.

[0142] Referring to FIG. 8, at time t0, segment decode line SG0 activehigh and sense amplifier S/A activated cause a potential difference in abit line pair and segment I/O line pair SGI/O depending on the datastored in a memory cell selected.

[0143] At time t1, signal W-CSL activated turns on transistors TWI1 andTWI2 so that the write data transmitted from the I/O line pair istransmitted to segment I/O line pair SGI/O. It should be noted that thepotential of the I/O line pair is not transmitted because the I/O linepair is connected to segment I/O line pair SGIO/O directly but thepotential of the I/O line pair drives the transistors TWC1 and TWC2potentials.

[0144] Thus, if the potentials of the paired I/O lines are not fullyswung, each at its complementary level, they can be transmitted tosegment I/O line pair SGI/O. Thus, the time required for precharging theI/O line pair can be reduced after the transmission of data to segmentI/O line pair SGI/O, to allow for rapid operation.

[0145] From time t2, a sense amplifier which has received the write dataat its sense node starts to amplify the write data.

[0146] At time t3, signal W-CSL is inactivated to shut down the datacommunication from the I/O line pair to the segment I/O line pair.Responsively the I/O line pair is precharged to the power supplypotential Vcc level.

[0147] At time t4, the potential level of a word line and the level ofsignal BLIL are both driven to boosted potential Vpp. Responsively thesense node of the sense amplifier is coupled with a selected memorycell. At time t5, of sense amplifier driving signals, a p-channel MOStransistor driving signal SP further increases in level and an n-channelMOS transistor driving signal SN further decreases in level to allow thepotential level of the bit line pair to provide full swing. Since thepotential level of the word line has been increased to the boostedlevel, either high-level data or low-level data can be written in thememory cell with sufficient margin.

[0148] At time t6, the level of segment decode line SG0 starts totransition to an inactive state and the segment I/O line pair isdisconnected from the bit line pair. Then the word line is alsoinactivated.

[0149] At time t8, signal IOEQ transitions to an active state andsegment I/O line pair SGI/O is precharged to ground potential GND.

[0150] At time t9, equalization signal EQ transition to an active stateand the potential level of the bit line pair is precharged e.g. to the ½Vcc level. At time t10, the signals BLIL and BLIR levels are set to theintermediate potential.

[0151] It should be noted that in the standby state after time t10 theequalization signal EQ level may be a predetermined potential no morethan power supply potential Vcc. As a result, reducing the currentsupplying capability of a transistor of equalization circuit EQCKT0 orthe like in the standby can decrease any current leakage flowing fromthe power supply of the ½ Vcc potential via a bit line when the bit lineand some interconnect short-circuit, to decrease the power consumptionof the memory cell array.

[0152] Modification of Second Embodiment

[0153]FIG. 9 is a circuit diagram showing a configuration connecting asense amplifier portion and data line portion of a semiconductor memorydevice as a modification of the second embodiment.

[0154] The FIG. 9 configuration differs from the FIG. 6 configuration inthat transistors TPC1′ and TPC2′ for precharging a segment I/O line pairare both p-channel transistors and that the precharged potential levelof segment I/O line SGI/O is power supply potential Vcc.

[0155] The remaining configuration shown in FIG. 9 is similar to thecorresponding portion shown in FIG. 6 and the identical portions aredenoted by the same reference characters and the description thereofwill not be repeated.

[0156]FIG. 10 is a timing diagram for illustrating an operation of theFIG. 9 circuit connecting a sense amplifier portion and a data lineportion in read operation.

[0157] The FIG. 10 operation differs from the FIG. 7 operation in thatinitially at time t0, segment I/O line pair SGI/O is precharged to powersupply potential Vcc.

[0158] Thus, when segment decode signal SG0 is activated, the potentiallevel of the bit line pair and that of the segment I/O line pair arehigher than the precharged-level potential of the bit line pair, i.e. ½Vcc. Thus, while the FIG. 10 system does not reduce the time requiredfrom the point when the potential level of the word line starts tochange to the point when data is read, the FIG. 10 system canadvantageously drive a sense amplifier faster than e.g. when the senseamplifier is supplied with a ground potential via a transistor and theparasitic resistance of the sense amplifier cannot be neglected on thesource side.

[0159]FIG. 11 is a timing diagram for representing an operation of theFIG. 9 circuit connecting a sense amplifier portion and data lineportion in write operation and precharge operation.

[0160] The FIG. 11 operation is basically similar to the FIG. 8operation, except that the precharge level of segment I/O line pairSGI/O is power supply potential Vcc.

[0161] Third Embodiment

[0162]FIG. 12 is a schematic block diagram showing a configuration of aredundant circuit for substituting for a defective memory cell in thememory cell array in the semiconductor memory device configured as shownin FIGS. 1 and 2.

[0163] Referring to FIG. 12, a row spare region for substituting for arow of memory cells is provided at an outermost periphery of the memorycell array.

[0164] A spare cell in the column direction is provided at a boundarybetween banks of the memory cell array. Data each read on an I/O linepair are amplified by an amplifier 3010 (or a spare amplifier) and heldin a latch circuit 3020. The data in latch circuit 3020 is transmittedby a driver circuit 3030 provided for latch circuit 3020 to any data busDBS selected by a shift switch circuit 3040 (or a shift switch circuit3040 and a demultiplier 3050).

[0165]FIG. 13 is a schematic block diagram showing another configurationof the redundant circuit.

[0166] The FIG. 13 configuration differs from the FIG. 12 configurationin that a spare memory cell block for substituting for memory cell rowsis provided in a region separate from the memory cell array. Theremaining configuration shown in FIG. 13 is similar to the correspondingconfiguration shown in FIG. 12 and the description thereof will not berepeated.

[0167] Configuration of Shift Redundancy

[0168] Hereinafter, a configuration and operation for substitution witha redundant column by means of shift switch circuit 3040 will now bedescribed more specifically.

[0169]FIG. 14 is a schematic block diagram showing a configuration ofshift switch circuit 3040 in shift redundancy.

[0170] In the FIG. 14 configuration, two spare I/Os are provided at itscenter portion. The figure shows a configuration of a shift portionexisting between the data bus side and the read/write amplifier side,focusing on the spare I/O portion mentioned above.

[0171] The centered, two spare I/Os can each substitute for either amemory cell column corresponding to an upper I/O in the figure or amemory cell corresponding to a lower I/O in the figure. Furthermore, ifthere are two defects in the upper or lower group of I/O lines in thefigure, a shift operation performed for two stages can providesubstitution for the defects.

[0172] In order to do so, there are arranged a first shift portion forinitially performing a single-stage shift followed by a second shiftportion for performing a single-stage shift.

[0173] The first shift portion provides a one-stage shift upward for anupper I/O line in the figure and a one-stage shift downward for a lowerI/O line in the figure.

[0174] The second shift portion is basically similar in operation to thefirst shift portion, although the two spare I/Os each shift both upwardand downward.

[0175]FIG. 14 shows a connection prior to normal substitution. Beforesubstitution is provided or if any substitution is not required, theinitial connection is maintained. More specifically, regular and spareI/O lines are each connected to an originally correspondingconnection-node located exactly on the left side and the spare I/O isnot connected to any data bus.

[0176] If substitution requires both of the two spare I/Os to be shiftedupward, as shown in FIG. 15, both spare I/O-A and spare I/O-B areshifted upward in the second shift portion initially. A similar upwardshifting is also provided in the first shift portion to implement such aredundancy substitution as described.

[0177] If substitution requires both of the two spare I/Os to be shifteddownward, as shown in FIG. 16, both spare I/O-A and spare I/O-B areshifted downward in the second shift portion initially. A similardownward shifting is also provided in the first shift portion to achievethe redundancy substitution as described.

[0178] If substitution requires one spare I/O line to be shifted upwardand the other downward, as shown in FIG. 17, the first shift portion isnot subjected to shift operation while the second shift portion hasshifters on the upper side each shifted upward, and shifters on thelower side each shifted downward.

[0179]FIG. 18 is a schematic block diagram more specifically showing theconfiguration of shift switch circuit 3040.

[0180] To simplify the description thereof, focusing on theconfiguration including the lower spare I/O of the first shift portion,with a transistor for connection implemented with an n-channel MOStransistor, a fuse link arranged in parallel is laser-blown to providefixed change in connection.

[0181] Before substitution is provided or if substitution is notrequired, the initial connection (the condition that a complementary I/Oon the right side and a complementary I/O on the left side are connectedtogether one on one) is maintained. In determination of redundancyconnection, signal TR goes high and current is passed via a transistorhaving current controlled by a redundancy control circuit.

[0182] When the fuse link is unblown, a train of fuses 73-79 of the fuselink is set to ground potential GND and a train of fuses 72-78 of thefuse link goes high to maintain the connection described above. Itshould be noted that the dot line in the figure represents theconnection.

[0183] In this condition, in the figure the uppermost I/O hastransistors 56 and 57 turned on so that connection is made to animmediately left-hand connection node. Transistors 58 and 59 are turnedoff and the connection to the one stage below is shut off.

[0184]FIG. 19 shows a configuration providing substitution for a defectexisting in a memory cell column 84.

[0185] When a defect is caused for I/O line pair 84, fuse link portions76 and 77 corresponding to the defective point are laser-blown toprovide the change in configuration of shifting to the one stage belowrather than connecting to the defective point. It should be noted thatthe dot line represents connection.

[0186] In FIG. 20, an n-channel MOS transistor configured circuit isinstead configured of CMOS transistor to provide a fuse link portion ina single train. In place of a redundancy control circuit, a simpleresistive element is arranged to limit current. Furthermore, a transfergate of a connection portion is of CMOS to reduce the resistance of anI/O line. (The dot line represents connection.)

[0187]FIG. 21 shows that one-stage shift is achieved by laser-blowing afuse link portion at an unnecessary point.

[0188] In the figure, the dot line represents a connection in such anexample.

[0189]FIG. 22 shows an exemplary configuration capable of dynamicconnection change to suit the form of such a fixed change in connectionas described above for a multibank configuration.

[0190] In the multibank (multimat) configuration, an I/O line isarranged across over other banks (malts). Accordingly, when a differentI/O is rescued for each bank (or mat) the form of connection need bechanged.

[0191] Thus, shift information of the first shift portion and that ofthe second shift portion are changed according to a bank address (or mataddress) input.

[0192] First of all, a program device programming a defective addresscan be a laser-blown or electrically-fused fixed element, a sharedgeneral film, a non-volatile RAM configurations e.g. of flash ROM, orthe like.

[0193] A defective address is held for the first and second shiftportions in common.

[0194] The above information is transferred to a hatch arranged in acomparison portion when a chip or a bank is activated after power-on. Inother words, a defective address is read once after power-on or afterthe chip is activated. The timing at which the information istransferred is provided between a time point at which a power-on-resetis provided and a time point at which an operation of a column whichrequires comparing operation is performed. The configuration providingthe transfer described above includes parallel-transfer technique,serial transfer using a shift register, and the like.

[0195] For the transfer via a shift register, the latch in thecomparison portion is also included in the shift register as a portionthereof to facilitate the transfer operation. The transfer clock may begenerated internally by a ling oscillator of appropriate period or itmay be generated in response to an external clock.

[0196] The comparison portion compares a bank address (or mat address)input to information read from a ROM portion and uses the result ofmatch/mismatch to output information on substitution. The substitutioninformation is output as a signal encoding a location to be shifted Thissignal is decoded to change a shift condition. It should be noted thatthe fuse link portion disconnectable by laser beam in the shiftedconfiguration described above is formed from a MOS transistor and thedecode signal controls the turning on/off of a MOS transistorfunctioning as a switch.

[0197]FIG. 23 shows a configuration of a decoding portion and that of aMOS transistor portion.

[0198] More specifically, while in FIG. 18 a fuse element is used toswitch a connection path, FIG. 23 shows a concept that the fuse elementis substituted with a MOS transistor switch.

[0199] Information on I/O line's 256 shifted locations is represented bycombined, 16 signals which are decoded by a four-input NAND circuit NDi(i=1, 2, 3, . . . ) to determine a location at which the gate of a MOStransistor is turned off. Before the encoded signal is transmitted, thesignals are all precharged low and the gates of all MOS transistors areheld ON.

[0200] While the above description is provided with respect to the firstshift portion, the same configuration is basically applied to the secondshift portion. It is, however, different in that the spare I/O portionis switchable either upward or downward. To meet this, spare I/O-Aremains connected to the immediately left-hand thereof or is shifteddownward if encoded signals for upper shifted locations are all heldlow. By contrast, spare I/O-B remains connected to the immediatelyleft-hand thereof or is shifted upward if encoded signals for lowershifted locations are all held low.

[0201] In other words, the fact that upward or downward shifting is notrequired results in a connection being changed based on an estimationthat there is a possibility that a two-stage shift has been provided onthe opposite side.

[0202]FIG. 24 is a circuit diagram showing configuration of the portiondescribed above. When encoded signals from the lower side are processedby an NOR gate and determination is made that all of them are low,connection is made to the one stage above, i.e. a terminal immediatelyon the left hand of spare I/O-A.

[0203] Substitution for each I/O line can provide a redundantconfiguration serving as a multiple I/O output configuration. For aconventional configuration with n redundancies arranged for each block,redundancy must be arranged for each I/O. This unnecessarily increasesthe number of redundant portions and wastes area.

[0204] The two-stage shifting configuration can also handle a pluralityof defective locations to provide efficient substitution operation. Itshould be noted that while the above description has been provided fortwo-stage shift, more stages can be applied to provide redundancysubstitution of more I/O lines. Dynamically changing a form ofconnection also allows defective locations in a multibank configurationto be substituted bank by bank or mat by mat to further enhance theefficiency of substitution.

[0205] Fourth Embodiment

[0206]FIG. 25 is a schematic block diagram showing a configuration of aredundant memory array for substituting for a defective memory cell in aplurality of banks arranged in four rows and four columns in asemiconductor memory device according to a fourth embodiment of thepresent invention.

[0207] The FIG. 25 configuration is an array configuration having aplurality of spare memory blocks which can arbitrarily substitute for aconfiguration formed from a plurality of banks arranged in four rows andfour columns. In the FIG. 25 example, 16 banks of 4×4 are shown with anI/O line pair arranged across four banks arranged in the horizontaldirection. Of the data transmitted on the I/O line pair to an I/O switchportion, a block of required data is to be transmitted on a data bus viaa column switch.

[0208] Eight spare blocks SB1A to SB4B each include a plurality ofprogrammable redundant rows (spare rows). A redundant row substitutesfor not only a defect of banks sharing an I/O line but a row of a bankcorresponding to a different I/O line to enhance substitutionefficiency.

[0209] Initially, in order to enable substitution in a different bank, abank address to be substituted is programmed in a BAP portion and a rowaddress to be substituted in a RAP portion.

[0210] In this condition, when bank and row addresses input at rowaccess time match the programmed bank and row addresses a redundancydetermination portion 3010 outputs a match signal indicating thatredundancy substitution is performed.

[0211] In response to the match signal, a corresponding spare block'sspare word line is activated. Since redundancy determination operationand the like are controlled quite independently of the address decodingprocess in a normal bank, row access in a normal region and the processof redundancy determination and redundancy activation and the like cansimultaneously proceed in parallel. Thus access time can be reduced, ascompared with the conventional, typical system of completing aredundancy determination process before resuming an access to a memorycell to be selected.

[0212] Then, in activating column select line CSL of a spare regionthrough column access an I/O line different from that for a normalregion must sometimes be used. Accordingly, a bank address for columnaccess need be compared to a bank address used in row access.

[0213] Accordingly, initially, a bank address of a bank subjected toredundancy substitution at row access time is held in a latch circuit asa subject to be compared at column access time.

[0214] A bank address input at column access time is compared to thebank address held in the latch circuit. When the addresses match, columnselect signal CSL in a spare block associated with redundancydetermination portion 3010 outputting a result indicating the match isactivated while column select signal CSL in the normal region isinactivated simultaneously.

[0215] Also, in controlling IO switch portion 3100 for connecting dataon an I/O line to a data bus, when a bank address input at column accesstime is compared to a bank address held in the latch circuit and theaddresses match, an IO switch portion receiving data on an I/O lineassociated with redundancy determination portion 3010 outputting aresult indicating the match is activated while an ID switch portionreceiving data on an I/O line of the normal region is inactivated.

[0216] In other words, when a bank address of an address hitting adefective address at row access time matches a bank address of a columncommand input at column access time, column bank match determinationcircuit 3100 inactivates a block to which the original memory cellcolumn belongs and circuit 3110 indicates that a memory cell columnbelonging to a spare block with a spare word line activated is selected.

[0217] When a bank address of an address hitting a defective address atrow access time matches a bank address of a column command input atcolumn access time, column bank match determination circuit 3110 alsoinactivates a block to which the original I/O line pair belongs andcircuit 3100 indicates that an I/O line belonging to a spare block witha spare word line activated is selected.

[0218] For each of 4×2 redundant rows contained in each of associated,two spare blocks, redundancy determination portion 3010 includes a BAPportion for programming a bank address and a BAC portion for comparingan input bank address to a programmed bank address, a RAP portion forprogramming a row address and a RAC portion for comparing an input rowaddress and a programmed row address, and a HIT portion outputting asignal HIT indicative of redundancy-determination result. That is, (4×2)×4 sets of the BAP portions and the like are provided in total.

[0219]FIG. 26 is a circuit diagram for illustrating a configuration ofthe BAP portion for programming a bank address and the BAC portion forcomparing an input bank address to a programmed bank address in the FIG.25 redundancy determination portion 3010.

[0220] The BAP portion includes program devices PR0 to PRn eachoutputting a complementary signal of a predetermined level when either afuse element F10 or F11 is cut. It should be noted that a bank addressis of (n+1) bits and there are provided (n+1) program devices, wherein nrepresents a natural number.

[0221] The BAC portion includes an activation program portion 3200 fordesignating whether the BAC portion is to be used, a precharge portion3300 for precharging an internal node np, and a comparison portion 3400performing an operation comparing data stored in the BAP portion and abank address input.

[0222] The activation program portion includes a fuse element FR0provided between power supply potential Vcc and node n1, an n-channeltransistor 3202 provided between node n1 and ground potential GND andhaving a gate potential controlled by a power-on-reset signal /POR, aninverter 3206 receiving the level of node n1 as an input, and ann-channel transistor 3204 connected in parallel with transistor 3202 andhaving a gate potential controlled by an output from inverter 3206.

[0223] When fuse element FR0 is cut, transistor 3202 is turned on inresponse to activated power-on-reset signal /POR at power-on andinverter 3206 provides a high-level output. Responsively, transistor3204 is turned on and the high level of the output from inverter 3206 isheld.

[0224] Precharge portion 3300 includes an NAND circuit 3302 receiving aredundant-row precharge signal and an output from inverter 3206, and ap-channel transistor 3304 having a gate potential controlled by anoutput of NAND circuit 3302 for charging node np in comparison portion3400.

[0225] Comparison portion 3400 includes transistors T01 and T02 providedin series between node np and ground potential GND. The transistor T01gate receives an output PA0 from program device PR0 and the transistorT02 gate receives an internal bank address signal BAddR0.

[0226] Comparison portion 3400 also includes transistors T03 and T04provided in series between node np and ground potential GND. Thetransistor T03 gate receives an output /PA0 from program device PR0 andthe transistor T04 gate receives an internal bank address signal/BaddR0.

[0227] Other programming devices PR1 to PRn are each provided with asimilar configuration between internal node np and ground potential GND.

[0228] Comparison portion 3400 also includes a detector 3402 activateddepending on a level of a Signal output from inverter 3206 and receivingthe level of input node np as an input, and an inverter 3404 receivingand inverting an output from detector 3402 and outputting a bank hitsignal BAHIT.

[0229] Signals PA0 and /PA0 to PAn and /PAn output from program devicesPR0 to PRn are also output to column bank match determination circuit3110.

[0230]FIG. 27 is a circuit diagram for illustrating a configuration ofthe RAP portion for programming a row address and the RAC portion forcomparing an input row address and a programmed row address in the FIG.25 redundancy determination portion 3010.

[0231] The configuration of the RAP and RAC portions is basicallysimilar to that of the BAP and BAC portions shown in FIG. 26, exceptthat programmed and compared addresses are row addresses and that aprogrammed address is not output to column bank match determinationcircuit 3110. Thus the identical portions are denoted by the samereference characters and the description thereof will not be repeated.

[0232]FIG. 28 is a schematic block diagram showing a configuration ofthe FIG. 25 HIT portion.

[0233] The HIT portion includes an AND circuit 3802 receiving bank hitsignal BAHIT indicating that an input bank address signal matches aprogrammed bank address signal and a row hit signal RAHIT indicatingthat an input row address signal matches a programmed row addresssignal, and AND circuit 3804 receiving an output from AND circuit 3802and a flag ACT activated by a command ACT.

[0234] An output level of AND circuit 3804 is transmitted to a latchcircuit 3806, and in response to an output from latch circuit 3806 adecoder 3808 performs operation to select a spare word line.

[0235] The HIT portion also includes a flip-flop circuit 3810 set inresponse to the output from AND circuit 3802, an inverter 3812 invertingan output of flip-flop circuit 3810 to output a spare match flag SHITF,and an AND circuit 3814 receiving the output from AND circuit 3802 and aflag PC activated in response to a precharge command to output a signalinstructing spare-block resetting operation.

[0236] The output level of flip-flop circuit 3810 is reset in responseto the output from AND circuit 3814.

[0237]FIG. 29 is a circuit diagram for illustrating a configuration ofcomparison circuit 3120 of the FIG. 25 column bank match determinationcircuit 3110.

[0238] Comparison circuit 3120 determines whether a bank addressdesignated when a column address is input matches a bank address storedin program devices PR0 to PRn in the BAP portion.

[0239] More specifically, comparison circuit 3120 includes an NANDcircuit 3122 receiving a redundant-row precharge signal and signalSHITF, and a p-channel transistor 3124 having a gate potentialcontrolled by an output from NAND circuit 3122 to charge node np.

[0240] Comparison circuit 3120 also includes transistors T01 and T02provided in series between node np and ground potential GND. Thetransistor T01 gate receives output PA0 from program device PR0 and thetransistor T02 gate receives internal bank address signal BAddR0 when acolumn address is input.

[0241] Comparison circuit 3120 also includes transistors T03 and T04provided in series between node np and ground potential GND. Thetransistor T03 gate receives output /PA0 from program device PR0, andthe transistor T04 gate receives internal bank address signal /BAddR0when a column address is input.

[0242] Other programming devices PR1 to PRn are each provided with asimilar configuration between input node np and ground potential GND.

[0243] Comparison circuit 3120 also includes a detector 3126 activatedin response to a level of a signal output from inverter 3206 andreceiving the internal node np level as an input, and an inverter 3128receiving and inverting an output from detector 3126 and outputting acolumn bank hit signal CBHIT.

[0244]FIG. 30 is a schematic block diagram for illustrating aconfiguration of a selection indicating circuit 3140 responsive to acomparison result from comparison circuit 3120 for indicating in whichone of four groups, each including four banks laterally arranged, of the4×4 banks shown in FIG. 25 column select operation and IO switch 3100operation are to be performed.

[0245] Referring to FIG. 30, selection indicating circuit 3140 includesOR circuits 3150.1 to 3150.4 respectively provided for groups GR1 to GR4each formed from four banks arranged laterally in FIG. 25, each ORcircuit receiving eight signals CBHITs in the associated, two spareblocks. For example, OR circuit 3150.1 receives as an input eightsignals CBHITs corresponding to spare blocks SB1A and SB1B(corresponding to eight spare rows.)

[0246] Selection indicating circuit 3140 includes a four-input ORcircuit 3160 receiving outputs from OR circuits 3150.1 to 3150.4, aninverter 3162 inverting an output from OR circuit 3160, AND circuits3170.1 to 3170.4 each receiving at one input node a signal NCSindicative of normal column select operation and at the other input nodean output from inverter 3162, and OR circuits 3180.1 to 3180.4 receivingthe outputs from OR circuits 3150.1 to 3150.4, respectively, at oneinput node and the output from inverter 3162 at the other input node tooutput a signal CGA instructing their respective groups GR1 to GR4 toselect a column and also instructing associated IO switch 3100 toperform I/O line pair select operation.

[0247] If an address signal does not HIT any spare addresses, columnselection according to a normal column address is activated. If anaddress signal hits any spare address, selection is activated accordingto a spare column address.

[0248] With the configuration described above, one of spare blocks SB1Ato SB4B can be substituted for any defective memory cell row or columnin any of the banks arranged in four rows by four columns so as toenhance conversion efficiency.

[0249]FIG. 31 is a schematic block diagram showing another example ofthe redundant configuration provided in a unit of a memory cell array.In the FIG. 31 configuration, a latch circuit is provided as a redundantelement at an end of the unit of the memory cell array. A bank addressand a row address are compared to each other at a redundancy comparisonand determination portion. When the addresses match, the latch circuitis accessed. The redundancy determination operation may be provided inparallel with an access operation to a memory cell in a normal region,as has been described above, so that access time can be shorter thanwhen a redundancy-determination result is obtained before starting anaccess operation to a memory cell in a normal region.

[0250] In the FIG. 31 configuration, the latch circuit holding dataeliminates the necessity of activating a word line in access.

[0251] In both of read and write operations, when a programmed addressand an input address match, corresponding column select signal CSLactivated allows data to be read and written.

[0252] Configuring a redundant circuit from a latch circuit such as asense amplifier is dissimilar to configuring a DRAM from memory cells,eliminating the necessity of word line activation. Thus, accessoperation may simply be performed for the regular memory cell region atrow access time, whether a location accessed is normal or defective. Inother words, redundancy determination operation is not required at rowaccess time, so that row access time can be reduced.

[0253] Furthermore, determining at column access time whether a regularbank (or memory cell mat) is to be accessed or a redundant portionconfigured from a latch circuit is to be accessed only requiresdetermining a bank address of a defective address or a mat address.Thus, access time is not increased.

[0254] The redundant portion configured from a latch circuit can also beused for different purposes other than defect substitution.

[0255] For example, the redundant portion can be used as a register fortemporarily saving data, a temporary saving register in refreshoperation, and the like. The address of data temporarily saved can beprogrammed in a redundancy determination portion and an accessed addressand the programmed address can be compared to each other, as in theredundancy determination, so that when the both addresses match, thetemporarily saved data may be accessed.

[0256] Configuration of Word Line Select Circuit and Column SelectCircuit for Multibank

[0257]FIGS. 32 and 33 are schematic block diagrams for illustratingarranging a main word driver and subordinate decode driver for selectinga word line when banks are arranged in rows and columns.

[0258] It should be noted that a subordinate decode driver correspondsto a driver circuit for driving select line SL in the FIGS. 2 and 3.

[0259] In FIG. 32, main word driver MWD and subordinate decode driverSDD are arranged in the x direction while a main word line and selectline SL extend in the y direction to transmit a signal to an activatedbank.

[0260] In FIG. 33, a main word driver is arranged along a line extendingin the x direction while a subordinate decode driver is arranged along aside extending in the y direction.

[0261] In both FIGS. 32 and 33 configurations, functionally a bank isselected depending on a logical product of main word line MWL and selectline SL. It should be noted, however, that which wiring layer's metalwiring configures a signal line for memory selection is determined basedon selection speed depending on wiring delay. Since the top-layer'smetal wiring does not necessarily have minimum signal delay, the metalwiring layers used to implement a wiring for transmitting a word lineselect signal, a wiring for transmitting a column select signal, and adata line are determined depending on the configuration, design ruleprocess conditions and the like of the device of interest.

[0262] FIGS. 34-38 are schematic block diagrams for illustratingarranging a column select line driver circuit CSD and column decodecircuit CDD when banks are arranged in rows and columns.

[0263] In FIG. 34, a column select line extends in the x direction and aplurality of banks arranged in the x direction receive a signal fromcolumn select line driver CSD in common.

[0264] Thus, to provide simultaneous, multiple data outputs from aplurality of banks in the FIG. 34 configuration, it is necessary toactivate a plurality of column select line (rivers to simultaneouslyactivate a plurality of banks arranged in the x direction.

[0265] When a plurality of banks are arranged in the direction of acolumn select line with the column select line shared by a plurality ofbanks, a column selection is provided in the plurality of bankssimultaneously. Thus, simultaneous output of multiple data requirescontriving I/O line arrangement or using a select gate connecting an I/Oline and a bit line pair together depending on a logical product of abank select signal and a column select signal to prevent collision ofdata.

[0266] The FIG. 35 configuration is basically similar to the FIG. 34configuration, although each bank is selected in response to a signaloutput from a column decode driver to individually select from aplurality of banks arranged in the x direction.

[0267] In the FIG. 36 configuration, a column decode driver is arrangedalong a side in the x direction in the FIG. 35 configuration.

[0268] In FIG. 37, column select line driver CSD and column decodedriver CDD are both arranged along a line in the X direction. In FIG.38, a column select line driver is arranged along a side in the xdirection and a column decode driver along a side in the y direction.

[0269] FIGS. 39-42 are schematic block diagrams for illustrating variousarrangements of a data line in a memory cell array having bank arrangedin rows and columns.

[0270] In the FIG. 39 configuration, an I/O line is shared by arelatively short sense amplifier band within a single bank. With thisconfiguration, data is output in a direction orthogonal to a word line.The arrangement of an I/O line for each relatively short unit allowsmultiple data to be output simultaneously.

[0271] In the FIG. 39 configuration, a data line is arranged in the xdirection.

[0272] In the FIG. 40 configuration, a data line is arranged in the xdirection, as shown in FIG. 39, and the data is also shared by two banksadjacent mutually in the y direction.

[0273] In the FIG. 41 configuration, a data line is arranged in the ydirection. That is, an I/O line is arranged in the direction of a wordline for each sense amplifier band.

[0274] In the FIG. 42 configuration, an I/O line pair is shared by arelatively short sense amplifier band, as is similar to FIG. 39, beforedata is transmitted in a direction orthogonal to a word line (i.e. inthe x direction) on a second I/O line and then also in the direction ofthe word line (i.e. in the y direction).

[0275] Hereinafter, exemplary wiring arrangements capable of readingmultibit data simultaneously will now be described based on combinationsof the arrangements of a word line select circuit, a column select lineand a data line as described above.

[0276] FIGS. 43-60 are conceptual views each showing a combination of anarrangement of a word line select circuit, that of a column select lineand that of a data line.

[0277] In the FIG. 43 example, main word line MWL, select line SL and adata line are arranged in the y direction and column select line CSL inthe x direction. The configuration of the data line is similar to thatshown in FIG. 42.

[0278] This configuration requires data line DL to be independentbetween sense amplifiers to avoid data collision between banks in thedirection of column select line CSL.

[0279] In this example, multibit data output is provided for byincreasing the number of column select lines CSLs.

[0280] In FIG. 44, column decode line CDL allows banks arranged in the xdirection to be individually selected to prevent such data collisionbetween banks as described in FIG. 43. Data line DL is arranged in the xdirection.

[0281] In the FIG. 45 example, column select line CSL and column decodeline CDL are arranged in the x direction, and main word line MWL, selectline SL and data line DL are arranged in the y direction.

[0282] In this example, as is similar to FIG. 43, the number of columnselect lines CSLs should be increased to output multibit data.

[0283] In the FIG. 46 configuration, column select line CSL and dataline DL are arranged in the x direction and main word line MWL, selectline SL and column decode line CDL are arranged in the y direction.

[0284] In the FIG. 47 example, column select line CSL is arranged in thex direction while main word line MWL, select line SL and columndecode-line CDL, and data line DL are arranged in the y direction.

[0285] In the FIG. 48 configuration, a data line is arranged in the xdirection, while main word line MWL, select line SL, column select lineCSL and column decode line CDL are arranged in the y direction.

[0286] With this configuration, banks adjacent mutually in the ydirection can be simultaneously selected to facilitate outputtingmultibit data.

[0287] In the FIG. 49 configuration, main word line MWL, select line SL,column select line CSL and column decode line CDL, and data line DL arearranged in the y direction.

[0288] In this configuration, outputting multibit data requires the dataline to be independent for each sense amplifier band unit.

[0289] With this configuration, all control signals and data can beadvantageously input from a single direction to facilitate connection toperipheral circuitry.

[0290] In the FIG. 50 configuration, main word line MWL, select line SLand column select line CSL are arranged in the y direction, and columndecode line CDL and data line DL in the x direction.

[0291] This configuration is suitable for outputting multibit data,since data can readily be read simultaneously from a plurality of bankadjacent mutually in the y direction.

[0292] In the FIG. 51 configuration, only column decode line CDL isarranged in the x direction and the other lines in the y direction.

[0293] In FIG. 52, main word line MWL and data line DL are arranged inthe y direction, and column select line CSL and select line SL in the xdirection.

[0294] In the FIG. 53 configuration, only main word line MWL is arrangedin the y direction, and select line SL, column select line CSL, columndecode line CDL and data line DL in the x direction.

[0295] In the FIG. 54 configuration, main word line MWL and data line DLare arranged in the y direction, and select line SL, column select lineCSL and column decode line CDL in the x direction.

[0296] In the FIG. 55 configuration, main word line MWL and columndecode line CDL are arranged in the y direction, and column select lineCSL, select line SL and data line DL in the x direction.

[0297] In the FIG. 56 configuration, main word line MWL, select line SLand column decode line CDL, data line DL are arranged in the ydirection, and column select line CSL in the x direction.

[0298] In the FIG. 57 configuration, main word line MWL, column selectline CSL and column decode line CDL are arranged in the y direction, andselect line SL and data line DL in the x direction.

[0299] In the FIG. 58 configuration, main word line MWL, column selectline CSL, column decode line CDL and data line DL are arranged in the ydirection, and only select line SL in the x direction.

[0300] In the FIG. 59 configuration, main word line MWL and columnselect line CSL are arranged in the y direction, and select line SL,column decode line CDL and data line DL in the x direction.

[0301] In the FIG. 60 configuration, main word line MWL, column selectline CSL and data line DL are arranged in the y direction, and selectline SL and column decode line CDL in the x direction.

[0302] Any of the signal-line arrangements described above allowsmultibit data to be output simultaneously.

[0303] It should be noted that any particular limitations are imposed onwhich ones of multi-layered wirings used in any specific configurationof a semiconductor memory device are respectively used as signal linesMWL, SL, CSL, CDL, DL) required for these accesses. Depending on theprocess for manufacturing a semiconductor memory device, the resistance(a sheet resistance) per unit length of a wiring layer and thecapacitance per unit length of the wiring layer and the wiling lengthand tolerance in signal delay of the wiring are referred to to allot asignal to the wiring layer.

[0304] For example, for a metal wiring layer of four levels with thebottom-level layer of tungsten (W) wire and the upper three layers ofcopper (Cu)based metal wire, if the lowest one of the three layers ofcopper (Cu)-based metal wire has a small wiring thickness and aresistance value set higher than those of the other two layers, thewires of the lower two of the four layers are higher in resistance thanthose of the upper two layers. Thus, the wires of the lower two layersare not suitable for long-distance wiring and thus often applied torelatively short-distance wiring in the FIGS. 32-60 configurationsdescribed above.

[0305] For example, in the FIG. 39 data line configuration, data inactivated bank are initially collected on a short-distance data line andultimately output to a long-distance data line laid out in a directionorthogonal to the short-distance data line. Thus in this configuration,the portion of the short-distance data line described above may berelatively high in resistance is thus more likely to be implementedusing a wiring of a lower layer.

[0306] Although the present invention has been described and illustratedin detail, it is dearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor memory device comprising: amemory cell array having a plurality of memory cells arranged in rowsand columns, and divided into a plurality of memory cell blocks in rowsand columns; a plurality of main word lines in a row direction of saidmemory cell array, shared by a plurality of said memory cell blocksarranged in the row direction; a plurality of subordinate word linescorresponding to memory cell rows in said memory cell blocks, having afirst plurality of subordinate word lines provided for each said mainword line; a main row select circuit provided for said memory cellarray, selectively activating said main word in response to an addresssignal; a subordinate row select circuit provided for said memory cellarray, indicating a selected subordinate word line of said firstplurality of subordinate word lines in response to said address signal;a block select circuit indicating a selected memory cell block inresponse to said address signal; a plurality of block select linesactivated in response to a selection indication from said block selectcircuit; and a plurality of drive circuits each provided for saidsubordinate word line, each driving a potential of an associatedsubordinate word line in response to an indication from said subordinaterow select circuit and to activation of an associated said block selectline and said main word line, each said drive circuit including a firstswitch circuit transmitting a potential level from said main word linein response to activation of said block select line, and a hold circuitactivated in response to an output level from said first switch circuitand to an indication from said subordinate row select circuit to holdselection indicating information for said associated subordinate wordline and drive a potential of said associated subordinate word; whereinsaid main row select circuit and said block select circuit reset a levelof said main word line and a level of said block select line after saidselection indicating information is transmitted to said hold circuit. 2.The semiconductor memory device according to claim 1 , wherein each saidmemory cell block is a bank independently capable of reading and writingdata therein.
 3. The semiconductor memory device according to claim 2 ,further comprising a plurality of select lines transmitting anindication from said subordinate row select circuit to said drivecircuit, wherein: said first switch circuit includes a first MOStransistor provided between said main word line and an informationholding node and having a gate potential controlled by said block selectline; and said hold circuit includes a second MOS transistor providedbetween said select line and said associated subordinate word line andhaving a gate potential controlled by a potential of said informationholding node, and a third MOS transistor provided between saidassociated subordinate word line and said information holding node andhaving a gate potential controlled by said select line.
 4. Thesemiconductor memory device according to claim 3 , wherein with anactivation level of said main word line and said block select linecorresponding to a first potential level, said select line is boosted toa second potential level after said block select line is reset in level,said second potential level being higher than said first potentiallevel.
 5. The semiconductor memory device according to claim 1 , furthercomprising: a plurality of bit line pairs corresponding to memory cellrows of said memory cell block; a plurality of data line pairs eachprovided for every second plurality of memory cell columns of saidmemory cell array, communicating data with a selected memory cell; and aplurality of select circuits capable of selective data communicationbetween said data line pair and an associated said second plurality ofbit line pairs.
 6. The semiconductor memory device according to claim 5, wherein said select circuit includes the second plurality of secondswitch circuits provided for said second plurality of bit line pairs,respectively, selectively rendered conductive, and a data transmissiongate receiving an output from said second plurality of second switchcircuits, responsive to a potential level of a selected bit line pairfor driving a potential of an associated said data line pair, saidtransmission gate having a fourth MOS transistor coupled between one ofsaid data line pair and a predetermined power supply potential andhaving a gate potential driven by one of said selected bit line pair,and a fifth MOS transistor coupled between the other of said data linepair and said predetermined power supply potential and having a gatepotential driven by the other of said selected bit line pair.
 7. Thesemiconductor memory device according to claim 6 , further comprising: aplurality of segment data line pairs coupling said select circuit andsaid data transmission gate together; a first precharging circuitprecharging said segment data line pair to a first precharged level instandby state; and a second precharging circuit precharging said bitline pair to a second precharged level in standby state.
 8. Thesemiconductor memory device according to claim 5 , further comprising aredundant memory cell row provided at an end of said memory cell array.9. The semiconductor memory device according to claim 5 , furthercomprising: plurality of redundant memory cell columns provided for saidmemory cell array; a plurality of redundant data line pairs provided forredundant memory cell columns, for communicating data with a selectedredundant memory cell; a data bus shared by a plurality of said memorycell blocks, for communicating data with said memory cell block; and adata-transmission switching circuit switching connection between saiddata line pair and said redundant data line pair, and said data busdepending on whether said redundant memory cell column has substitutedfor said memory cell column.
 10. A semiconductor memory devicecomprising: a memory cell array having a plurality of memory cellsarranged in rows and columns, and divided into a plurality of memorycell blocks in rows and columns; a row select circuit provided for saidmemory cell array, selecting said memory cell row in response to anaddress signal; a block select circuit indicating a selected memory cellblock in response to said address signal; a plurality of redundant;memory cell blocks provided independently of said memory cell blocks;and a redundancy determination circuit previously storing a memory cellblock and address having a defective memory cell to select a redundantmemory cell in said redundant memory cell block when a memory celldesignated by an address signal corresponds to said defective memorycell.
 11. The semiconductor memory device according to claim 10 ,wherein each said memory cell block is a bank independently capable ofreading and writing data therein.
 12. The semiconductor memory deviceaccording to claim 11 , said memory cell blocks being divided in m×n,wherein m and n are each a natural number, there being provided at leastm said redundant memory cell blocks arranged in parallel with a linealong which m said memory cell blocks are arranged, further comprising:a plurality of data line pairs along a direction along which n saidmemory cell blocks are arranged, shared by said memory cell block andsaid redundant memory cell block; a data bus communicating data withsaid memory cell block and said redundant memory cell block; and adata-transmission switching circuit arranged in parallel with a linealong which m said memory cell blocks are arranged, selectivelyconnecting said plurality of said line pairs and said data bus together.13. The semiconductor memory device according to claim 11 , saidredundancy determination circuit holding a location of a redundantmemory cell block including a redundant memory cell having substitutedfor said defective memory cell, further comprising a block matchdetermination circuit controlling said data-transmission switchingcircuit depending on which redundant memory cell block has a memory cellsubstituted when an input address signal is a defective address.
 14. Thesemiconductor memory device according to claim 13 , wherein: saidredundancy determination circuit selects a redundant memory cell row ofsaid redundant memory cell blocks in response to a row address signal;and said block match determination circuit controls saiddata-communication switching circuit according to a location of aredundant memory cell block selected in response to said row address,and according to a column address signal.